This application claims the benefit of Korean Patent Application No. 2002-0031678, filed Jun. 5, 2002, and Korean Application No. 2002-0040092, filed Jul. 10, 2002, the disclosures of both of which are hereby incorporated herein by reference in their entirety as if set forth fully herein.
The present invention relates to integrated circuit devices and fabrication methods therefor, and more particularly to integrated circuit capacitor devices and fabrication methods therefor.
Integrated circuit capacitors are widely used in integrated circuit devices. For example, in Dynamic Random Access Memory (DRAM) devices, integrated circuit capacitors may be used to store charge thereon, and thereby store data. As the integration density of integrated circuit devices, such as DRAM devices, continues to increase, it may be desirable to maintain sufficiently high storage capacitance while decreasing the area of the integrated circuit substrate that is occupied by each capacitor.
In order to increase the amount of capacitance per unit area of the integrated circuit substrate, it is known to use three-dimensional capacitor structures that can increase the effective area thereof. One type of three-dimensional capacitor structure is a cylindrical capacitor. Cylindrical capacitors are well known to those having skill in the art and are described, for example, in U.S. Pat. No. 6,258,691, entitled Cylindrical Capacitor and Method for Fabricating Same, assigned to the assignee of the present application, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
As is well known to those having skill in the art, an integrated circuit capacitor generally includes a first or lower electrode, also referred to as a storage node, a dielectric layer on the first or lower electrode, and a second or upper electrode on the dielectric layer opposite the first or lower electrode. In a cylindrical capacitor, at least part of the lower electrode is cylindrical in shape.
A conventional semiconductor memory device having cylindrical capacitor lower electrodes and a conventional method of manufacturing the same will be described with reference to FIGS. 1 and 2. As shown in FIGS. 1 and 2, an interlevel insulating layer 110 is deposited on a semiconductor substrate 100 having semiconductor devices (not shown) such as metal oxide semiconductor (MOS) transistors. Storage node contact plugs (hereinafter referred to as contact plugs) 115 are formed in the interlevel insulating layer 110.
Capacitor lower electrodes 120a and 120b having cylindrical shapes are formed on the contact plugs 115 and predetermined portions of the interlevel insulating layer 110. The capacitor lower electrodes 120a and 120b are composed of bottoms 120b, which are electrically connected to the contact plugs 115 and sidewalls 120a, which extend from the bottoms 120b upward, to a predetermined thickness, so as to be perpendicular to the bottoms 120b. The capacitor lower electrodes 120a and 120b, i.e., the bottoms 120a enclosed by the sidewalls 120a, may be circular, elliptical, or polygonal such as rectangular. Spaces in the sidewalls 120a are vacant and open. A dielectric layer and capacitor upper electrodes are formed on the resultant structure so as to complete the capacitors.
A method of manufacturing the capacitor lower electrodes 120a and 120b that are cylindrically shaped will now be briefly described. First, an etch stopper (not shown) and a mold oxide layer (not shown) are sequentially deposited on the interlevel insulating layer 110 having the contact plugs 115. The mold oxide layer is formed to a thickness of about 15,000 xc3x85. The mold oxide layer and the etch stopper are selectively etched using photolithography and an etching process so as to define areas in which capacitor lower electrodes will be formed. The contact plugs 115 are exposed in the areas in which the capacitor lower electrodes will be formed. Next, a conductive layer (not shown) is conformally deposited to a predetermined thickness in the areas in which the capacitor lower electrodes will be formed and on the mold oxide layer, and then a buffer dielectric layer (not shown) is deposited on the conductive layer.
Thereafter, the buffer dielectric layer and the conductive layer are etched until the surface of the mold oxide layer is exposed so as to separate nodes of the conductive layer. For the etching process, Chemical Mechanical Polishing (CMP) and/or dry etch back is used. Remaining portions of the buffer dielectric layer and the mold oxide layer are removed using wet etching so as to make the capacitor lower electrodes 120a and 120b cylindrical.
Unfortunately, capacitors including the capacitor lower electrodes (120a and 120b) which are cylindrical may have the following problems. As the density of the devices increases, areas of the bottoms 120b may continue to be reduced. Thus, if heights of the sidewalls 120a do not increase, capacitors having a desired capacitance may not be obtained. However, when increasing the heights of the sidewalls 120a in order to increase the capacitance, the entire arrangement of devices formed under and over the capacitors may change. Moreover, if the heights of the sidewalls 120a are too great, the ratio of the heights of the sidewalls 120 to the widths of the bottoms 120b may be too great. Due to this aspect ratio, the capacitor lower electrodes 120a and 120b may become slanted, which may cause the semiconductor device to have defects.
According to some embodiments of the present invention, integrated circuit capacitor electrodes are manufactured by depositing a first layer, which may be a mold oxide layer, on a semiconductor substrate. The mold oxide layer is patterned so as to define areas in which capacitor lower electrodes will be formed. A conductive layer is conformally deposited on the areas in which capacitor lower electrodes will be formed and on the patterned mold oxide layer. A second layer, which may be a buffer dielectric layer, is formed on the conductive layer. Nodes of the conductive layer are separated by etching the buffer dielectric layer and the conductive layer. The conductive layer is further etched between the mold oxide layer and the buffer dielectric layer to form recessed portions of the conductive layer.
The process of forming the recessed portions may be performed in situ with or apart from a process of separating the nodes of the conductive layer. In some embodiments, the process of forming the recessed portions and the process of etching the buffer dielectric layer and the conductive layer are performed using dry etch back.
According to other embodiments of the present invention, there is also provided a method of manufacturing a semiconductor memory device including capacitor lower electrodes composed of lower and upper storage electrodes. The upper storage electrodes, which are dual cylindrical type electrodes composed of bottoms and first and second sidewalls having different sizes, are formed on the lower storage electrodes, nodes of which are separated and recessed. The bottoms are positioned on the sidewalls of the lower storage electrodes and are formed between lower edges of the first sidewalls and lower edges of the second sidewalls but not inside of the lower edges of the second sidewalls.
In some embodiments, when forming the lower storage electrodes, a first conductive layer is conformally deposited in the areas in which the lower storage electrodes will be formed and on the mold oxide layer. A first buffer layer, which may be a first buffer dielectric layer, is deposited on the first conductive layer. The first buffer dielectric layer and the first conductive layer are etched to separate nodes of the first conductive layer. Recessed portions are formed by further etching the first conductive layer.
In some embodiments, etching the first conductive layer is performed using dry etch back. Etching the first conductive layer and forming the recessed portions may be sequentially performed in situ. The first conductive layer may be formed of a material having good etch selectivity to the mold oxide layer and first buffer dielectric layer.
In some embodiments, when forming the upper storage electrodes, the mold oxide layer and the first buffer dielectric layer deposited beside the recessed portions are etched to define areas in which the upper storage electrodes of dual cylindrical type are formed. A second conductive layer is conformally deposited in the areas in which the upper storage electrodes are formed and on the mold oxide layer and the buffer dielectric layer. A second buffer layer, such as a second buffer dielectric layer, is deposited on the second conductive layer. The upper storage electrodes are formed by etching the second buffer dielectric layer and the second conductive layer. Remaining portions of the mold oxide layer, the first buffer dielectric layer, and the second buffer dielectric layer are removed.
In some embodiments, the thickness of the lower storage electrodes is within the range of about 100-500 xc3x85 and the thickness of the upper electrodes is within the range of about 100-400 xc3x85. After the upper storage electrodes are formed, a dielectric layer adjacent to the lower capacitor electrodes may be formed. Next, capacitor upper electrodes adjacent to the dielectric layer may be formed, to complete the capacitor.
According to still other embodiments of the present invention, there is also provided a semiconductor memory device including bilayered capacitor lower electrodes having lower storage electrodes and upper storage electrodes. The lower storage electrodes are single cylindrical type electrodes, and the upper storage electrodes are dual cylindrical type electrodes composed of bottoms and first and second sidewalls having different sizes. The bottoms are positioned on the sidewalls of the lower storage electrodes and are formed between lower edges of the first sidewalls and lower edges of the second sidewalls, but not inside of the lower edges of the second sidewalls.
The capacitor lower electrodes may be formed of polysilicon or a metal material. In some embodiments, the height of the upper storage electrodes accounts for 10-90% of the height of the capacitor lower electrodes. In some embodiments, the thickness of the lower storage electrodes is within the range of about 100-500 xc3x85 and the thickness of the upper storage electrodes is within the range of about 100-400 xc3x85.
The circumferential shapes of the lower and upper storage electrodes may be polygonal, elliptical, or circular. A dielectric layer which is arranged adjacent to the capacitor lower electrodes may be further formed. Capacitor upper electrodes which are arranged adjacent to the dielectric layer may be further formed.
Integrated circuit capacitor electrodes according to other embodiments of the present invention comprise a first conductive ring on a face of an integrated circuit substrate and including a first ring axis that extends orthogonal to the face. A second conductive ring is provided on the first conductive ring opposite the substrate, and including a second ring axis that extends orthogonal to the face. A third conductive ring also is provided on the first conductive ring opposite the substrate, and including a third ring axis that extends orthogonal to the face. The third ring is located at least partially within the second ring. A conductive layer electrically connects the first, second and third rings. In some embodiments, the first conductive ring, the second conductive ring and/or the third conductive ring are ellipsoidal (for example elliptical or circular) or polygonal (for example square or hexagonal) in shape. Moreover, in other embodiments, the first, second and third conductive rings are coaxial. In still other embodiments, the perimeter of the second ring is greater than that of the first ring, and the perimeter of the third ring is less than that of the first ring. In still other embodiments, the conductive layer comprises a fourth ring that extends between the second and third rings adjacent the first ring, but not within the third ring.
Other embodiments of the present invention provide integrated circuit capacitor electrodes, which may function as intermediate structures in fabrication methods that were described above, and which comprise an integrated circuit substrate including a face and an insulating layer on the face of the integrated circuit substrate. A conductive ring is provided in the insulating layer. The ring includes a ring axis that extends orthogonal to the face, first and second ring walls, a ring floor adjacent the face and a ring roof remote from the face. The insulating layer includes a trench therein that exposes the ring roof but does not expose the ring walls. In some embodiments, the conductive ring is ellipsoidal or polygonal in shape.
According to yet other embodiments of the present invention, integrated circuit capacitor lower electrodes are manufactured by forming a first layer, such as a mold oxide layer, on a semiconductor substrate. The mold oxide layer is patterned to define areas in which the capacitor electrodes are formed. A conductive layer is conformally deposited in the areas in which the capacitor electrodes are formed and on the patterned mold oxide layer. A buffer layer, such as a buffer dielectric layer, is formed on the conductive layer. The buffer dielectric layer and the conductive layer are etched to separate nodes of the conductive layer. Recessed portions are formed between the mold oxide layer and buffer dielectric layers by further etching the conductive layer. The mold oxide layer and the buffer dielectric layer are etched deeper than the recessed portions to define areas in which caps will be formed. A dielectric layer is formed in the areas in which the caps will be formed. The caps are formed by planarizing the mold oxide layer, the buffer dielectric layers, and the dielectric layer. At least some of a remaining portion of the mold oxide layer and at least some of a remaining portion of the buffer dielectric layer are removed.
When defining the area in which the caps are formed, the mold oxide layer between adjacent capacitor lower electrodes may be patterned in all widthwise and lengthwise directions so that the mold oxide layer remains higher than the recessed portions. Also, the mold oxide layer between adjacent capacitor lower electrodes may be patterned in a first direction such that the mold oxide layer remains deeper than the recessed portions and in a second direction such that the mold oxide layer remains higher than the recessed portions. In some embodiments, the circumferential shapes of the capacitor lower electrodes are elliptical, and the first direction is the minor axis direction of the circumferential shapes.
In other embodiments, the dielectric layer is formed of a dielectric material such as a silicon nitride layer or the like. The caps may be formed using chemical mechanical polishing and/or dry etch back. The mold oxide layer, the buffer dielectric layer, and the dielectric layer are patterned so as to be higher than or equal height to the capacitor lower electrodes.
According to other embodiments of the present invention, a semiconductor memory device includes a semiconductor substrate, a plurality of cylindrical capacitor lower electrodes which are formed in an array on the semiconductor substrate, and caps which are formed so as to enclose upper portions of sidewalls of the capacitor lower electrodes. Adjacent caps may be separated from each other or may be connected to each other only in one direction. Also, the capacitor lower electrodes may be elliptical, in which case the caps may be connected to each other in the minor axis direction of the capacitor lower electrodes. The caps may be alternatively formed on the capacitor lower electrodes. In some embodiments, the caps are formed of a dielectric material such as silicon nitride (SiN). The heights of the caps may be equal to or higher than the heights of the capacitor lower electrodes.
Integrated circuit capacitor electrodes according to other embodiments of the invention include an integrated circuit substrate having a face and a conductive ring on the face of the integrated circuit substrate. The conductive ring includes a ring axis that extends orthogonal to the face, first and second ring walls, a ring floor adjacent the face, and a ring roof remote from the face. A conformal insulating cap is provided on the roof and extending on the first ring wall only partially to the floor. In other embodiments, the conformal insulating cap also extends on the second ring wall only partially to the floor. In still other embodiments, the conductive ring is ellipsoidal or polygonal in shape.